1. Field of the Invention
The present invention generally relates to an analog-to-digital converting system, and more particularly, to an analog-to-digital converting system by using a cascade of flash analog-to-digital converter and a successive approximation analog-to-digital converter.
2. Description of Related Art
Analog-to-digital converters (ADC) have various architectures, for example, flash analog-to-digital converters (flash ADC), pipeline analog-to-digital converters (pipeline ADC), and successive approximation analog-to-digital converters (SA ADC), all of which respectively have suitable application fields.
Flash ADC is typically the fastest, but has the highest implementation cost. In an N-bit ADC, there are 2N possible digital number outputs. A total of 2N−1 boundaries define the analog input ranges corresponding to the digital number outputs. In flash ADC, 2N−1 analog reference signals are generated. An input is simultaneously compared to each reference signal. The 2N−1 comparators produce digital output signals which are decoded to produce the desired digital output number.
Flash ADC is fast because the input-to-output delay includes the reaction times of one comparator stage and the subsequent decoding logic. Flash ADC is costly to implement, because the number of analog reference signals and comparators grows exponentially with N.
SA ADC is considerably slower than flash ADC, but has a much lower implementation cost for large N. In successive approximation, a binary-tree search is performed on the possible digital output numbers. The binary-tree search proceeds in a sequence of N approximation steps. At each step, a possible digital output number is passed to an N-bit digital-to-analog (D/A) converter, which produces a corresponding analog value. This value is compared to the analog input signal. The result of the comparison is used to select a new possible digital number value for the following step.
With respect to components, an N-bit SA ADC requires one comparator, an N-bit D/A converter, and logic circuits for directing the search and storing the results. The converter and the comparator can be re-used for each step of the search. The speed of the SA converter depends on N and on the settling times of the comparator, the D/A converter, and the logic circuits. For instance, a 12-bit SA ADC would require 12 comparison steps of 12 separate 12-bit D/A conversion results, while an 8-bit SA A/D conversion would require only 8 comparison steps of 8 separate D/A conversion results.
The principle disadvantages of prior art flash ADCs are that while they are fast, they typically need a large number of components which use a great deal of chip space and which consume a large amount of power. The exponential increase in component counts and power consumption of flash ADCs limits the number of bits for which such converters are economically feasible to use. The principle disadvantages of SA ADCs are that while they have low component cost and are economical for higher precision than are flash ADCs, they are quite slow and make inefficient use of the resources consumed. It is therefore an object of the present invention to provide a novel ADC which is fast and which has low complexity.